Tunable Fault Tolerance via Test and Reconfiguration

The advent of reconfigurable hardware as a computing medium creates a multi-dimensional design space where trade-offs between power, speed, cost, and reliability are now possible. Dynamic reconfiguration allows these trade-offs to be made on-line to adapt to various environmental changes. Furthermore, the cost of designing reliable circuits is greatly reduced since varying levels of reliability can be added to any circuit, even if it was not originally designed to run reliably, either at the time of application start-up or during application execution. This paper briefly discusses two ways that reconfiguration and hardware virtualization [1,2] can be used to produce or modify the level of circuit reliability. The first method addresses Single-Event-Upset (SEU) faults by allowing the level of redundancy in the circuit to be dynamically varied. Detection and retry mechanisms provide a level of reliability similar to that of triple modular redundancy, at a cost of only two times (instead of the traditional three times) the original hardware or 50% performance. The second technique described provides reliability in the presence of local hardware faults. This technique works by rotating a built-in self-test (BIST) operation around the reconfigurable hardware periodically, while continuing to execute the application. Both methods may be used to modulate the amount of reliability provided on an application-by-application basis or during application execution. The former case is used when a single field programmable gate array (FPGA) is used for many different applications and applies to both current commercial FPGAs as well as more modern architectures. When an application is loaded on the reconfigurable hardware, a level of reliability is specified. The latter case, which is more powerful, is suited only to newer architectures which support high-speed reconfiguration such as PipeRench [1,2].